The present invention relates to fabrication processes for semiconductor devices. More particularly, the present invention relates to a method of manufacturing semiconductor devices for providing the formation of conductive lines or plugs by using tungsten, copper, polysilicon, and the like, and minimizing the step-height of interlayer dielectric layers by etching thin films on the semiconductor substrate using a specific etching composition and spin etching methods. The present invention also relates to an etching composition for manufacturing semiconductor devices, and semiconductor devices made by these processes.
Recently there has been an increased demand for fine pattern formation technology for semiconductor devices and the use of multi-layered circuit structures for semiconductor devices as they become more highly-integrated. In other words, the surface structures of semiconductor devices are becoming more and more complicated, to the point that the step-height between layers can cause malfunctions in the fabrication process of semiconductor devices.
In a photolithography process from among the various fabrication processing steps, a photoresist pattern is formed on the semiconductor substrate by coating a wafer with a photoresist. A mask having circuit-forming elements is aligned on the wafer, and an exposure process is carried out by irradiating the photoresist on the wafer with light.
Semiconductor devices with relatively large critical dimensions i.e., the smallest dimension to be fabricated, and a low-layered structure can cause a few problems. However, with the finer patterns and multi-layered structures currently used on semiconductor substrate, it is more difficult to exactly focus between the upper position and the lower position of the step-height between layers in the exposure process. As a result, precise pattern formation is hard to achieve.
Therefore, planarization methods for minimizing the step-height between layers have become more important. Various planarization methods such as silicon-on-glass (SOG) layer deposition, etch back, or reflow, etc. have been employed in order to overcome the above problems, but these methods have other problems associated with them. Another method for planarization is the Chemical Mechanical Polishing (CMP) method.
The CMP method has been developed as a planarization process that operates across the whole surface of the wafer. When the CMP method is applied to a semiconductor device manufacturing process, the removal rate and the uniformity of planarization are important CMP parameters.
In the case where a silicon dioxide (SiO.sub.2) layer is planarized using an oxide layer CMP process, the property of the silicon dioxide (SiO.sub.2) is changed into a hydrophillic subject to H.sub.2 O permeability by the reaction with alkali slurry. Water intruded into the silicon dioxide (SiO.sub.2) operates to disconnect the connection chains of the silicon dioxide (SiO.sub.2). The silicon dioxide (SiO.sub.2) is then removed by a physical mechanism through the use of an abrasive.
In the case where a metal layer is planarized using a CMP process, however, the chemical reaction on the surface of the metal layer by an oxidant inside the slurry creates a metal oxide layer. This metal oxide layer is removed by the mechanical (physical) friction of the abrasive with the uppermost layer of the uneven pattern.
FIG. 1 is a schematic representation showing the conventional CMP apparatus for manufacturing semiconductor devices.
Referring to FIG. 1, the CMP apparatus comprises, a polishing head 102, a polishing table 104, and a polishing pad 108. The CMP process is carried out on the polishing table 104. The polishing pad 108 is formed on the polishing table 104 and holds a semiconductor substrate 100. A slurry is then supplied from a slurry supply line 106 and is used to polish the semiconductor substrate 100. The polishing head 102 secures the semiconductor substrate 100 to the polishing pad 108 and is movable in a rotational direction.
The polishing pad 108 comes in contact with the semiconductor substrate 100 in the CMP process. The semiconductor substrate 100 is rotated by the polishing head 102, and the slurry is supplied on the polishing pad 108. The slurry and the surface of the semiconductor substrate 100 react with each other, which causes the semiconductor substrate 100 to be polished by the polishing pad 108.
FIGS. 2 to 7 are cross sectional views showing a manufacturing process for semiconductor devices in order to describe conventional processing sequences for forming a tungsten plug, including the use of a CMP process. Processes for forming both a tungsten plug portion and an align mark are shown simultaneously.
The semiconductor device shown in FIGS. 2 to 7 is divided into a cell portion (C), formed of components of electric circuitry, and a peripheral portion (P), formed of components of align marks, scribe lines, etc.
As shown in FIG. 2, an oxide layer 114 is formed as a dielectric layer on a semiconductor substrate 110 having a plurality of local patterns 112 formed apart from each other. The local patterns 112 can each include a polysilicon pattern or metal pattern as a conductive layer. The oxide layer 114 is a silicon dioxide layer (SiO.sub.2) formed by a conventional Chemical Vapor Deposition (CVD) process, although a phosphosilicate (PSG) layer or a borophosphosilicate (BPSG) layer may also be used as a dielectric layer between the polysilicon pattern layers or between the metal layers. At this time, the oxide layer 114 is formed on both the cell and peripheral portions.
As shown in FIG. 3, the oxide layer 114, which is initially uneven because of the presence of the local pattern 112, is planarized using the CMP apparatus shown in FIG. 1 and described above.
As shown in FIG. 4, contact holes 116 are formed by a typical photolithography and etch process by coating the oxide layer 114 with a photoresist, forming a photoresist pattern, and then etching the oxide layer 114 using the photoresist pattern as an etch mask. At this time, a peripheral hole 118, used for an align mark or a scribe line, is formed in the oxide layer 114 in the peripheral region (P) with a diameter bigger than that of the contact holes 116.
As shown in FIG. 5, a dual titanium/titanium nitride (Ti/TiN) layer is formed on the whole surface of the oxide layer 114 as a barrier layer 120 before a tungsten layer is formed. The dual Ti/TiN barrier layer 120 includes a Ti layer 120a and a TiN layer 120b. The Ti layer 120a is formed using a conventional sputtering method or a CVD method, and the TiN layer 120b is formed using a typical sputtering method. The barrier layer 120 reduces the contact resistance of the tungsten layer, and improves the adhesiveness of the oxide layer 114 and the tungsten layer. In addition, during a later process for removing the tungsten layer, the barrier layer 120 is used as stopper layer. At this time, the barrier layer 120 is formed both over and in the contact holes 116 and the peripheral hole 118.
As shown in FIG. 6, a tungsten layer 122 is formed over the whole oxide layer 114 having a thickness sufficient to bury the contact holes 116 and at least partially fill the peripheral hole 118. The peripheral hole 118 has a bigger diameter than that of the contact hole 116 of the cell part, however, and so the peripheral hole 118 of the peripheral portion is not fully filled with the tungsten layer 122, but instead only has its bottom and sidewalls covered.
As shown in FIG. 7, the semiconductor substrate 110 having the tungsten layer 122 formed thereon is fixed on the polishing head 102 of the CMP apparatus of the FIG. 1, and the polishing pad 108 contacts with the tungsten layer 122 while the metal layer slurry is supplied from the slurry supply line 106. The polishing head 102 is then rotated to remove the upper portion of the tungsten layer 122 on the barrier layer 120 such that the lower portion of the tungsten layer 123 remains inside the contact holes 116. At this time, however, the lower portion of the tungsten layer 123 also remains on the bottom and sidewalls of the peripheral hole 118. The remaining tungsten layer 123 in the peripheral hole 118 (i.e. the align mark or scribe line) may later cause the generation of particles in a following photolithography process, thereby weakening the alignability of the photolithography process.
The tungsten plug formation process should typically be conducted after the planarization of the interlayer dielectric (ILD) layer. Therefore, when the CMP process is added to the planarization for the surface of the semiconductor wafer, the CMP process decreases the productivity of the manufacturing and increases the expense of the semiconductor device cost because of the short period allowed for the exchange of the polishing head and the slurry.
In addition, the dry each back process used during the formation of the tungsten plug increases the contact resistance and the worst electrical characteristics of the transistors because of the associated electrical charge-up of plasma.
Therefore, a demand has arisen to develop a method to address the above problems. We therefore provide a method to solve the above problems to improve efficiency and productivity of semiconductor devices manufacturing.